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* ddc is a registered trademark of vesa. applications desktop crt displays desktop lcd displays other desktop pc displays external crt displays for notebook computers features 1) 1kbit serial eeprom with configuration of 128 words 8 bits. 2) supports i 2 c bus. 3) supports ddc1/ ddc2 interfaces for monitor ids. 4) supports clock frequencies of 100khz and 400khz. 5) switching from ddc2 to ddc1 enabled using mode pin. 1 standard ics id rom for crt displays supporting plug & play bu9881 / BU9881F the bu9881 / BU9881F is a 1k bit eeprom conforming to the standardized interface that enables plug & play on crt displays. recommended operating conditions power supply voltage input voltage v in v cc parameter symbol v v unit 2.7 ~ 5.5 limits 0 ~ v cc absolute maximum ratings (ta = 25?) applied voltage power dissipation bu9881 BU9881F pd storage temperature operating temperature voltage for various pins * 1 reduced by 5.0mw for each increase in ta of 1 c over 25 c. * 2 reduced by 3.5mw for each increase in ta of 1 c over 25 c. * if input exceeds the absolute maximum ratings, the device may break down. v cc parameter symbol tstg topr ?0.3 ~ + 6.5 limits ?65 ~ + 125 ?40 ~ + 85 ?0.3 ~ v cc + 0.3 mw v unit c c v 500 * 1 350 * 2
2 standard ics bu9881 / BU9881F block diagram 8bit 7bit 7bit data register slave-word address register address decoder 1,024 bit eeprom array high voltage generator power supply voltage detection 1 mode n.c. n.c. control circuit start stop ack gnd v cc vclk scl sda 2 3 4 8 7 6 5 pin descriptions mode transmit-only mode switching pin (pulled down when used in open state) n.c. not connected gnd reference voltage of 0v for all input / output scl serial clock input pin for i 2 c mode vclk clock input pin for transmit-only mode v cc connect the power supply i i i pin name 1 2, 3 4 sda slave and word address serial data input / output i / o 5 6 7 8 pin no. function s the sda pin is nch open drain output, and should be used with an external pull-up resistor added. i / o
3 standard ics bu9881 / BU9881F electrical characteristics (unless otherwise noted, ta = ?40 to + 85?, vcc = 2.7v to 5.5v) measurement circuits v cc v ol 3.0ma v cc sda gnd data set when output is low v fig. 1 low output voltage measurement circuit v cc i li i lo v cc mode, vclk sda, scl gnd a v in = 0 ~ v cc v out = 0 ~ v cc fig. 2 input / output leakage current measurement circuit v cc i cc v cc sda gnd a scl, vclk mode write / read input 100 / 400 khz clock v cc fig. 3 current consumption measurement circuit v cc v cc isb v cc sda mode gnd a scl vclk fig. 4 standby current measurement circuit input high level voltage 1 v ih1 parameter symbol measurement circuit (scl, sda) input low level voltage 1 v il1 (scl, sda) input high level voltage 2 v ih2 (vclk) input low level voltage 2 v il2 v cc = 4.5 ~ 5.5v (vclk) v cc = 2.7 ~ 4.5v (vclk) input high level voltage 3 v ih3 (mode) input low level voltage 3 v il3 (mode) output low level voltage v ol i ol = 3.0ma(sda) fig.1 input leakage current 1 i li1 v in = 0v ~ v cc (scl ?sda ?vclk) fig.2 input leakage current 2 i li2 v in = 0v ~ v cc (mode) fig.2 output leakage current i lo v out = 0v ~ v cc (sda) fig.2 operating current consumption i cc v cc = 5.5v, twr = 10ms fig.3 standby current i sb v cc = 5.5v, mode = gnd vclk ?sda ?scl = v cc fig.4 min. 0.7v cc 2.0 0.8v cc ?1 ?1 ?1 max. 0.3v cc 0.8 0.4 0.4 0.4 1 15 1 3 30 unit v v v v v v v m a m a m a ma m a conditions
4 standard ics bu9881 / BU9881F operation timing characteristics (unless otherwise noted, ta = ?40 to + 85?) start condition hold time start condition setup time input data setup time parameter data clock low time sda / scl rise time sda / scl fall time clock frequency data clock high time input data hold time unit high-speed mode v cc = 4.5 ~ 5.5v standard mode v cc = 2.7 ~ 5.5v ns m s m s m s output data delay time output data hold time stop condition setup time bus release time prior to start of transfer t hd : sta t su : sta symbol t hd : dat t su : dat t high t low t r t f f scl t pd t dh t su : sto t buf m s m s m s m s m s m s m s khz m s max. 0.9 0.3 0.3 400 internal write cycle time effective noise elimination interval (scl, sda pins) t wr t i ms ns 50 10 min. 100 0.6 0.6 1.3 0 0 0.6 0 0.6 0 1.3 max. 3.5 1.0 1.0 100 10 min. 250 4.0 4.7 4.7 0 0 4.7 0 4.0 0 4.7 transmit ?only mode parameter vclk low time w mode transition time w power up time for transmission vclk output delay time vclk high time unit high-speed mode v cc = 4.5 ~ 5.5v standard mode v cc = 2.7 ~ 5.5v symbol tvhigh tvlow tvhz tvpu tvaa ns ns m s ns m s max. 500 500 min. 0.6 1.3 max. 0 0 500 500 min. 4.0 4.7
5 standard ics bu9881 / BU9881F circuit operation s basic operation the bu9881 / BU9881F is equipped with two modes, a normal i 2 c bus mode (bi-directional mode) and a transmit- only mode. the transmit-only mode can be accessed by turning on the power supply to the ic, or by using the software to control the mode. in this mode, operation is synchronized to the clock input to vclk, and it is possible to read the contents of the eeprom memory from the sda pin. to switch from the transmit-only mode to the i 2 c bus mode, the clock signal that recognizes the switching of high to low is input to the scl pin. the i 2 c bus mode is effective following the edge of that clock. to switch from the i 2 c bus mode to the transmit-only mode, the software can be used to control the mode, or the power supply to the ic can be turned off and then on again. this switches back to the transmit-only mode. (1) description of mode pin functions as shown in the illustration below, the software can be used to control the mode pin, enabling switching from the i 2 c bus mode to the transmit-only mode. 1)transmit-only mode this command causes all of the data written to the eeprom to be read. after the transmit-only mode is entered, inputting the vclk clock causes the data to be read from the sda pin. the sda pin is in the "hi-z" state for the first nine clock signals input, and data is output sequentially, timed to the rise of the clock starting with the tenth clock. addresses are incremented automatically as clock pulses continue to be input to vclk, with the data from the next address being read in sequence. while this is being done, the null bit (high data) is output between the data of one address and that of the next address. when the power supply is turned on, and when the mode is switched from the i 2 c bus mode to the transmit-only mode, the output data for the transmit-only mode is synchronized to vclk as follows: last address data ? 0h address data ? 1h address data ??? and is incremented in sequence. (following the last address, processing shifts to the 0h address.) note: reading in the transmit-only mode should not be done until the power supply has stabilized. when switch- ing from the transmit-only mode to the i 2 c bus mode, assure the tvhz time before beginning communica- tions. set low for 2 m s or longer set high for 2 m s or longer transmit only mode mode scl i 2 c mode i 2 c mode fig. 5
6 standard ics bu9881 / BU9881F v cc scl vclk tvpu 12 910 d7 d7 d0 bit null tvaa high-z sda mode don't care 0h address last address fig. 6 2) i 2 c bus mode 1. start condition (start bit recognition) before executing the various commands, if sda is high, a start condition (start bit) must be in effect such that sda changes from high to low. this ic constantly detects whether or not the start condition (start bit) is fulfilled for the sda and scl lines. if this condition is not fulfilled, no commands will be executed. (refer to the section on synchronized data input / output timing.) 2. stop condition (stop bit recognition) when the various commands have been completed, a stop condition (stop bit) can be used to terminate the commands by raising sda from low to high if scl is high. (refer to the section on synchronized data input / output timing.) 3. precautions concerning the write command * the stop bit cannot be executed in the write mode, so data that has been transmitted cannot be written to the memory. 4. write protect in the i 2 c bus mode, the vclk pin can be used as a write protect control pin. when the vclk pin is high, the byte write and page write commands function, but when the vclk pin is low, these two writing commands are canceled.
7 standard ics bu9881 / BU9881F r / w set to 0: writing (0 is also set in order to specify a word address for random reading.) r / w set to 1: reading 1010 : don't care r / w scl (from m -com) sda ( m -com output data) sda (data output from this ic) acknowledge signal (ack signal) start condition 1 89 fig. 7 acknowledge signal (ack signal) response (when slave address is input for writing or reading) (2) device addressing the master address should be output first, followed by the start condition, and then the slave address. the first four bits of the slave address are used to recognize the device type. the device code for this ic is fixed at "1010". the next three bits of the slave address may be either high or low. the last bit of the slave address (r / w: read / write) is used to specify either writing or reading, and is as shown below. (3) ack signal this acknowledge signal (ack signal) is determined by the software, and indicates whether or not the data has been correctly transmitted. regardless of whether the address is a master or slave address, the device on the transmitter (sending signal) side (the m -com when a slave address is input for a write command or a read com- mand, and this ic when read command data is output) opens the bus after this 8-bit data is output. with a device on the receiving (reception) side (this ic when a slave address is input for a read command or write command, and a microcomputer when data is output for a read command), sda is set to low during the nine-clock cycle, and the acknowledge signal (ack signal) is output when 8-bit data is received. this ic output the acknowledge signal (ack signal) in the low state after a start condition and a slave address (8 bits) have been recognized. for other writing operations, the acknowledge signal (ack signal) is output in the low state each time that 8-bit data (word address or write data) is received. in the various reading operations, 8-bit data (read data) is output, and then the acknowledge signal (ack signal) in the low state is detected. if the acknowledge signal (ack signal) is detected and no stop condition is sent from the master (microcomputer) side, this ic continues to output data. if the acknowledge signal (ack signal) is not detected, this ic interrupts the transmission of data, recognizes a stop condition (stop bit), and terminates the reading operation. the ic then enters the standby mode. (refer to "fig. 7 acknowledge signal (ack signal) response.")
8 standard ics bu9881 / BU9881F ?reading of input is done at the rising edge of scl. ?output of data is synchronized to the falling edge of scl. i 2 c synchronous data input / output timing scl sda (input) sda (output) t r t hd: sta t hd: dat t su: dat t f t low t pd t dh t high t buf fig. 8 write cycle timing sda d0 ack scl mode ? vclk ? t wr write data stop condition start condition h l (n address) fig. 10 write cycle timing scl sda t su: sta t su: sto t hd: sta start bit stop bit fig. 9
9 standard ics bu9881 / BU9881F timing charts (1) write cycle scl start condition stop condition sda 11 0 00 0 0 0 0 slave address wa0 wa6 d7 d0 1 89 17 18 26 27 mode ? vclk ? : don't care write data ack signal (output) word address fig. 11 byte write cycle scl start condition stop condition sda 1 1 00 0 0 0 0 0 slave address wa6 wa0 d7 d0 d7 d0 9 18 27 54 mode ? vclk ? : don't care write data write data ack signal (output) word address n + 7 fig. 12 page write cycle 1) data is written to the address specified by the word address (n address). 2) after 8 bits of data are input, a stop bit is generated. this initiates writing of the data to the memory cell. 3) this command enables writing of 8 bytes of data. 4) this page write command is used to specify any of the first four bits (wa6 to wa3) of the word address. the address is incremented internally, and up to 8 bytes of data can be written to the last three bits (wa2 to wa0).
10 standard ics bu9881 / BU9881F (2) read cycle scl start condition stop condition sda 1 1 1 0 0 0 0 0 slave address read data ack signal (output) ack signal (input) d7 d6 d5 d2 d1 d0 1 1 8 9 18 mode ? vclk don't care fig. 13 current read cycle scl start condition start condition stop condition sda 10000 00 0 slave address word address slave address read data ack signal (input) wa6 wa0 1 0 0000 1 11 d7 d0 1 ack signal (output) mode? vclk don't care fig. 14 random read cycle 1) with this ic, an internal address counter circuit increments the address one address at a time, and stores in memory the last word address (n address) for which the write or read command was executed. 2) this command reads only the data of the word address (n +1 address) following the last word address to be writ- ten after the previous command has been executed. 3) if the ack signal low following d0 is detected and no stop condition is sent from the master (microcomputer) side, reading can be continued sequentially to the data of the next word address. [the entire 1 kilobit (128 words) can be read.] (refer to "fig. 15 sequential read cycle.") 4) to terminate this command, high is input for the ack signal following d0, and the sda signal rises at the high state of the scl signal (stop condition), terminating the command. 5) this command enables reading of the data at the specified word address. 6) if the ack signal low following d0 is detected and no stop condition is sent from the master (microcomputer) side, reading can be continued sequentially to the data of the next word address. [the entire 1 kilobit (128 words) can be read.] (refer to "fig. 15 sequential read cycle.") 7) to terminate this command, high is input for the ack signal following d0, and the sda signal rises at the high state of the scl signal (stop condition), terminating the command.
1. controlling the mode pin (pin 1) from the main controller as shown in the figure below, the mode pin can be controlled through the software to switch from the i 2 c bus mode to the transmit-only mode. 11 standard ics bu9881 / BU9881F slave address read data read data ack signal (output) ack signal (input) scl start condition stop condition sda 1 1 1 0 00 0 0 d7 d7 d0 d0 n + a mode ? vclk don't care fig. 15 sequential read cycle (example: for current reading) set high for 2 m s or longer set low for 2 m s or longer mode scl i c mode transmit only mode 2 i c mode 2 fig. 16 8) if the ack signal low following d0 is detected and no stop condition is sent from the master (microcomputer) side, reading can be continued sequentially to the data of the next word address. [the entire 1 kilobit (128 words) can be read.] 9) to terminate this command, high is input for the ack signal following any d0, and the sda signal rises at the high state of the scl signal (stop condition), terminating the command. 10) sequential reading is also possible with random reading. 11) with earlier ics, switching from the ddc1 (transmit-only) mode to the ddc2 (i 2 c bus) mode was possible only by turning off the power supply and then turning it on again. with the bu9881 / BU9881F, however, switching between the normal i 2 c bus mode and the transmit-only mode can be done by controlling the mode pin (pin 1).
12 standard ics bu9881 / BU9881F 2. controlling the mode pin (pin 1) through an attachment 100 m f 62k w mode n.c. n.c. gnd vcc vclk scl sda fig.17 as shown at the left, if there is no scl input for approxi- mately 2 seconds (min.) to 6 seconds (max.) after the ddc2 (i 2 c bus) mode has been terminated with the diode, resistor, and capacitor, the mode changes automatically to the ddc1 (transmit-only) mode. external dimensions (units: mm) 0.5 0.1 3.2 0.2 3.4 0.3 85 14 9.3 0.3 6.5 0.3 0.3 0.1 0.51min. 2.54 0 ~ 15 7.62 0.4 0.1 1.27 0.15 0.3min. 0.15 0.1 0.11 6.2 0.3 4.4 0.2 5.0 0.2 85 4 1 1.5 0.1 dip8 sop8 bu9881 BU9881F

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